05 / Developer tooling

AI-Assisted FirmwareValidation Skill Chain

A composable engineering workflow that turns firmware build, device programming, and communication checks into a traceable minimum acceptance loop.

01 What it solves

What it solves

Firmware validation often crosses separate tools, file formats, and physical test conditions. This project packages those steps as focused skills, then coordinates them through one workflow with structured output and clear failure boundaries.

02 Skill-chain flow

Skill-chain flow

01IAR project (.ewp)
02IAR build
03BIN or image export
04J-Link flash
05DLMS probe / read / write
06JSON result

03 Four composable skills

Four composable skills

iar-build-verify

Builds IAR projects, supports configuration selection and structured results, and can export a BIN beside the generated output.

iar-jlink-flash

Resolves project flash settings and programs OUT, BIN, or HEX images through J-Link, including controlled Open Flashloader support.

dlms-comm-debug

Runs a minimum DLMS communication check through probe, read, or write operations after programming.

firmware-workflow

Orchestrates the preceding steps, stops on failure, and combines step status, artifacts, and next actions into one JSON result.

04 Programming modes

Programming modes

project-auto

Uses the IAR project’s normal image-selection path after a successful build.

project-bin

Exports a BIN during build and requires that BIN for the programming step.

delivery-hex

Programs paired firmware and parameter HEX files in the fixed order: firmware first, parameter second.

05 Engineering decisions

Engineering decisions

Preflight and dry-run paths make tool resolution, target choice, and planned J-Link commands inspectable before a real write.
Programming requires explicit confirmation in the desktop CLI; target checks can remain read-only.
Non-ASCII delivery paths are staged to an ASCII temporary location for J-Link compatibility.
Failure short-circuiting keeps build, flash, and DLMS failures distinguishable instead of masking the first failed stage.

06 Verified scope & boundary

Verified scope & boundary

IAR build to BIN export and BIN programming have been exercised on a real project and target MCU.
The paired delivery-HEX path and its firmware-to-parameter order are implemented and connected to the main workflow.
Intermittent J-Link attach failures are reported as board power, SWD wiring, reset timing, or target-state conditions—not attributed to workflow logic.

IAR EWARM · SEGGER J-Link · PowerShell · Python · DLMS · JSON